1. Field
This invention relates generally to signaling formats and encoding, and more particularly to signaling formats and encoding used for communication with PHY interfaces.
2. Related Art
Currently IEEE 802.3bj allows the use of two different signaling formats in conjunction with 100 Gb/s backplane PHYs: pulse amplitude modulation (PAM4), and non-return to zero (NRZ). In general the 100 Gb/s standard, as described in IEEE 802.3bj splits a 100 Gb/s signal into multiple different lanes, with each lane operating at a fraction of the full 100 Gb/s frequency. For example, the 100 Gb/s signal can be spread across into four lanes, each running at about 25 Gb/s. Where the system side data lanes are formatted using an NRZ protocol, PHY interfaces are used to convert NRZ data on the system side to PAM4 on the line side, and conversely from PAM4 on the line side back to NRZ system side.
An example of an external PHY 100 is illustrated in prior art FIG. 1. PHY 100 includes an egress path 101, and ingress path 151, internal control/test paths 171, and automatic negotiation and PHY configuration block 173 as specified by various IEEE standards. As illustrated in FIG. 1, four lanes of NRZ data clocked at 25.78 Gb/s are received at serializer/deserializer (serdes) 103, which forms part of egress path 101. Serdes 103 performs the serializer/deserializer functions and transmits the data, still in four-lane NRZ signaling format, to the 100 G data path 105, which includes 40 Gb attachment user interface (XLAUI) Rx PCS 106, 100 G Tx PCS 108, FEC encoder 110, and PAM4 Tx 112. XLAUI Rx PCS 106 aligns, deskews, and descrambles the NRZ data, and serves as a retiming interface, which can change the number of lanes used to transmit the data, if needed. XLAUI Rx PCS 106 essentially decodes the NRZ data. 100 G Tx PCS 108 inserts alignment blocks into the deskewed data for later use by a receiver in deskewing the data. The FEC encoder 110 applies forward error correction techniques to the data, and sends the data to PAM Tx 112, which transcodes the FEC encoded data into the 256b/257b data blocks used by PAM4.
After the data has been encoded according to the PAM4 protocol, the data is sent to Tx AFE (analog front end) 107, which modulates the data at a rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane and physically puts the data onto the backplane trace. Thus, the data enters PHY 100 on the system side in an NRZ signaling format at 25.78 Gb/s, and leaves PHY 100 on the line side at between about 26.5 Gbps/per lane to 27.2 Gbps/per lane in a PAM4 format.
A similar procedure is performed, except in reverse, when PAM4 data is received on the line side of PHY 100 using ingress path 151 and converted to NRZ data for output on the system side of PHY 100. PAM 4 data is received at RX AFE 157, and sent through the 100 G data path 155 for conversion to NRZ and output by serdes 153. PAM4 RX 162 decodes the data from the PAM4 format, FEC decoder 160 uses the REC information as necessary to perform error correction functions, 100 G RX PCS transcodes the data from 512b/514b format to the 64b/66b format, and XLAUI TX PCS adds alignment blocks to the data for later deskewing and adjusts the number of lanes as needed.
Unfortunately, current techniques used to convert NRZ data to PAM 4 data can require a significant amount of overhead and processing time, thereby rendering the current techniques less than optimal.